Latch-based memory arrays such as master/slave latch-based arrays are a common ASIC element. These arrays may be two-dimensional such that the latches are arranged in rows and columns. The width of a row depends upon the array word size. For example, if the word size is 8 bits, a row would include eight slave latches. The depth of the array determines the column length: if the array stores 8 words, then each column would include eight slave latches. Each stored bit may correspond to an individual master/slave latch pair. But to save die space, it is known to use a single master latch for each column of slave latches. For example, FIG. 1 shows a column 101 in a latch-based memory 100 that includes a single master latch 105 that drives four slave latches 110. Each slave latch 110 in column 101 is in a corresponding row in the array, ranging from a row 0 to a row 3. If master latch 105 wasn't shared in this fashion, there would need to be three more master latches for column 101.
Each row of slave latches 110 is clocked by a corresponding row write clock 130 as produced by a row clock gating circuit (CGC) 120 for that row. Each row CGC 120 receives a write clock (WCLK) 125 that may be passed as the CGC's row write clock 130 if the row is active in a write operation. A row decoder or equivalent circuit (not illustrated) thus controls row clock gating circuits (CGCs) 120 depending upon whether a given row is active or inactive in a write operation. Should a row be inactive (no write operation for that row), the corresponding row CGC 120 gates its row write clock 130 by holding its row write clock 130 in a first clock state. Write clock 125 cycles between the first and second clock states to effect a write operation. For example, the first clock state may be ground (VSS) and the second clock state may be the power supply voltage VDD.
For illustration clarity, row CGCs 120 are shown receiving only the write clock (WCLK) 125 but in an actual implementation they would also receive the decoded word address from a word address decoder (or its equivalents). Analogous to the clocking for slave latches 110, each master latch 105 is clocked responsive to a master write clock 135 from a master clock gating circuit (master CGC) 150. But as known in the master/slave arts, master latches 105 are level sensitive to a first clock state for master write clocks 135 whereas slave latches 110 are level sensitive to a second clock state for their row write clocks 130. The gating action for row CGCs 120 is thus reversed as compared to the gating by master CGC 150. To gate its row write clock 130, a row CGC 120 holds its row write clock 130 in the first clock state since slave latches 110 will only latch for the second clock state. But master CGC 150 gates master write clock 135 by holding master write clock 135 in the second clock state since master latches 105 will only latch for the first clock state. Because memory 100 is written to a word at a time, master CGC 150 responds to the assertion of any word address in that all the master latches 105 are activated to latch their data input signal D during a write operation. Should a word address be asserted, master CGC 150 passes write clock 125 as master write clock 135 to the master latches 105. But if no word address is asserted (no active write operation for any of the rows) master CGC 150 gates write clock 125 by holding master write clock 135 in the second clock state.
To satisfy universal asynchronous reset (UAR) requirements, both master latch 105 and slave latches 110 in latch-based memory 100 are responsive to a reset signal (RST) 140. If reset signal 140 is asserted, the stored content for master latch 105 and slave latches 110 is reset accordingly. A scan path may be used to detect faults such as reset faults in latch-based memory 100. A test pattern can then be scanned in and scanned out of latch-based memory 100 as is known in the automatic test pattern generation (ATPG) arts. But note that there may be many instances of such two-dimensional latch-based memories in an integrated circuit. It would require a great deal of die area to set up a scan path that went through each and every row and column in all the latch-based arrays. Thus, it is conventional to implement a partial scan path through (for example) just the first row (denoted as row 0) and the last column in memory 100. Naturally, such a partial scan path can detect faults in the scanned row and column. But reset faults in un-scanned rows (e.g., rows 1, 2, and 3) are undetectable through a partial scan chain. For example, suppose there is a stuck-at-zero reset fault for a slave latch 110 in row 3. A partial scan chain that only passes through row 0 would be unable to detect such a fault.
The latched data outputs from the slave latches in column 101 are read though a read multiplexer 115. But faults in rows bypassed by a partial scan chain cannot be read through multiplexer 115 because the reset in a UAR system resets the address bits driving read multiplexer 115 to select for row 0. So the problem remains of numerous slave latches having untestable reset faults in partial scan chain systems. The partial chain scan cannot be lengthened to scan the un-scanned rows because of the excessive die demands.
Accordingly, there is a need in the art for master/slave latch-based memory arrays having improved design-for-test (DFT) features such that faults can be detected despite the use of a partial scan chain.